ASIC Verification at Video Processing ASIC Startup
By Joel Steinberg | July 30, 2007
ASIC Design and Verification engineers are needed for this exciting Video Processing ASIC Startup.
Job Description:
Looking for a Senior ASIC Verification Engineer to be a key member of the ASIC verification team. Responsibilities will include developing the verification methodology, selecting tools, test plans, and verification environment (test bench and scripts) for verifying the function of the ASIC. Strong communication skills are required to work closely with the ASIC design team and with systems engineering to help with all stages of verification from specification to testing silicon in the lab.
Job Requirements:
- Expert in Verilog for verification and be able to read designs
- Strong programming skills in C and object oriented programming (C++ or other OO language)
- Strong scripting skills in unix scripting languages (bsh,csh,etc) and Perl
- Working knowledge of Vera, System Verilog, SystemC, or assertions is desired.
- Experience with processor/DSP verification is desired.
- At least 7 years of ASIC verification experience is required
- BSEE/CS is required (MSEE/CS preferred)
- Strong teamwork and communication skills (written & verbal) are required.
Job Categories: ASIC Verification, Video Processing ASIC Startup |
ASIC Design Engineer at Video Processing ASIC Startup
By Joel Steinberg | July 30, 2007
ASIC Design Job Opening:
STARTUP- Video Processor ASIC for hot sector of consumer market with no competition.
I have some exciting news. I have just been contacted by the original founders of well known Terayon. They started Terayon in 1994. My company, Responsive Technology helped them staff their early design teams back then. They took Terayon Public in a very successful IPO in 1998 and built it up to a 8 BILLION DOLLAR company with 1500 employees by the year 2000.
The two founders who are brothers, Shlomo and Zaki Rakib, have left Terayon and recently received their first round funding for a brand new startup venture for a unique product that has no competition in the hot consumer market. They are in extreme stealth mode so I can not disclose more at this time. Long term funding will be no issue.
They are forming their early design team with excellent people.
We need ASIC Design Engineers and Verification Engineers.
This is going to be an extremely high profile startup once the word is out. A very rare opportunity. The track record of these founders is stellar and doors are opening for them at every turn, whether it be with vendors, potential clients, investors and VC, and top talent for their team. I recommend you jump at the chance to at least talk to them.
If you are interested, send your resume directly to me at joel@rt6.com so it will arrive the quickest and get immediate attention.
Joel Steinberg
President- Responsive Technology
Referral fees are also being offered ($3000) for names/emails submitted for the following:
ASIC design
FPGA design
ASIC/FPGA Manager
ASIC/FPGA Directors
HS Board design
Firmware/RT/Emb SW
SW QA (RT Embedded)
Analog/RFIC
Physical design/ CAD/ Mask/Layout
Please email me at joel@rt6.com to hear about and have immediate access to gthe hiring managers at other hot openings at Cisco, Marvell, and other hot startups in Silicon Valley.
Job Categories: ASIC Design Engineer, Video Processing ASIC Startup |
Video Processing ASIC Startup
By Joel Steinberg | July 30, 2007
STARTUP- Video Processor ASIC for hot sector of consumer market with no competition.
I have some exciting news. I have just been contacted by the original founders of well known Terayon. They started Terayon in 1994. My company, Responsive Technology helped them staff their early design teams back then. They took Terayon Public in a very successful IPO in 1998 and built it up to a 8 BILLION DOLLAR company with 1500 employees by the year 2000.
The two founders who are brothers, Shlomo and Zaki Rakib, have left Terayon and recently received their first round funding for a brand new startup venture for a unique product that has no competition in the hot consumer market. They are in extreme stealth mode so I can not disclose more at this time. Long term funding will be no issue.
They are forming their early design team with excellent people.
This is going to be an extremely high profile startup once the word is out. A very rare opportunity. The track record of these founders is stellar and doors are opening for them at every turn, whether it be with vendors, potential clients, investors and VC, and top talent for their team. I recommend you jump at the chance to at least talk to them.
Job Categories: Video Processing ASIC Startup |
Low Power Wireless Startup
By Joel Steinberg | July 30, 2007
Low Power Wireless Startup: (I will release the name later)
This innovative low power wireless startup developing a new class of wireless products for the home and enterprise markets. They develop ICs that enable dramatic reduction in power for low-power connectivity with a unique architecture and a complete focus on low-power design that enables true wireless connectivity — no plugs required. In many applications, simple coin-cell or alkaline batteries will be sufficient to drive devices with this startup’s ICs for years.
If you are interested, send your resume directly to me at joel@rt6.com so it will arrive the quickest and get immediate attention from the hiring manager.
Joel Steinberg
President- Responsive Technology
www.rt6.com (Bayareastartups)
JOB Descriptions:
Analog/RF Engineer: The incumbent will design, layout and test RF and analog circuits. He/she must be self-driven and able to work and interact with all levels of the team. In addition to design, the incumbent will be expected to innovate and file patent disclosures to help build up the inventory.
Requirement: Minimum M.S. degree and 5+ years of experience carrying out a circuit project from concept to silicon in school (Ph.D) or in industry.
Recruiter notes: Seek wireless RF IC Designer - prefer CMOS technology but won’t exclude other (bipolar, etc). a) bandgap bias circuits, (b) low noise amplifiers, (c) mixer, (d) VCO, (e) LO (local oscillator) buffer, (f) ADC (analog-to-digital converter), (g) DAC (digital-to-analog converter), (h) frequency synthesizer, (i) PA (power amplifier),
Chip Lead (this would be the entire analog and RF section of a transceiver chip
IC = whole system – responsible for whole analog and RF section of transceiver ship = analog + digital.
Tools used: Regarding RF IC design: Look for Cadence, specifically Spectre RF, Ultrasim and RFDE (RF design environment); Look for ADS (Agilent). Regarding layout: Look for Cadence Virtuoso and Virtuoso XL (many RF IC designers do their own critical layout, something to look for, and rely on employee or contractor layout for less critical but voluminous layout load). Regarding verification: Look for Mentor Calibre.
Other Openings at this startup:
Test Engineer: The incumbent will be involved in planning, coordinating and conducting design verification and production testing of wireless integrated circuits. Must be skilled with state of the art test equipment for laboratory characterization, must possess strong data collection methodology and be detail oriented.
Requirement: Minimum B.S. degree and 7+ years of experience bringing products into volume production.
Recruiter notes: This is a Lab Test person as opposed to Production Test Engr. Will be on site working in lab validating the silicon we get back. Must know detailed RF Analog measurements and be skilled at taking measurements and evaluating results using advanced test equipment like RF transceiver measurements, use spectrum, network, modulation analyzers, bit error rate test sets, digital oscilloscopes, noise filter meters, etc. We want a lab specialist - more debug and as opposed to coding. Must understand and know how to use lab equipment.
Layout Engineer:
The incumbent will have strong skills in designing, organizing, verifying and modifying high performance analog, mixed signal and RF integrated circuits in a fast paced environment. Must be able to devise and implement solutions to complex layout constraints.
Requirement: A.S./B.S. degree and 10+ years experience bringing products into volume production.
CAD Engineer :
The incumbent will have strong demonstrated skills to specify and select CAD tools and computer systems for analog, digital, mixed signal and RF IC design, layout and verification. Must have strong working knowledge of submicron CMOS technology file development and maintenance.
Requirement: Minimum B.S. degree and 10+ years of experience bringing products into volume production.
Sr. Software Quality Assurance Engineer:
The incumbent will be involved in the early phase of design to prepare for testing of the software. This includes suggesting hooks in software, building up the test/lab infrastructure, and writing code to activate/test our product. It includes, for example, writing code to use our product with various access points. Requirement: Minimum B.S. degree and 10+ years of experience bringing products into volume production.
Recruiter notes: Need SQA from embedded micrcontroller SW world - 68000 Assembly (or lower level) and C programming. Core experience needs to be how to devise, run and evaluate test suites for that SW at that level. Could be a firmware piece of writing drivers for host processor outside of chip that communicates with chip. SQA person will confirm end to end assurance that we are doing right thing.
Referral fees are also being offered ($3000) for names/emails submitted for the following:
ASIC design
FPGA design
ASIC/FPGA Manager
ASIC/FPGA Directors
HS Board design
Firmware/RT/Emb SW
SW QA (RT Embedded)
Analog/RFIC
Also: Physical design/ CAD/ Mask/Layout
Please email me at joel@rt6.com to hear about and have immediate access to the hiring managers at other hot openings at Cisco, Marvell, and other hot startups in Silicon Valley.
Job Categories: Low Power Wireless Startup |
Cisco Position: Architect/RTL/ASIC
By Joel Steinberg | July 30, 2007
Cisco ASIC/Architect Position:
Cisco Systems for their CPP group.
You will participate in the design and development of high-performance network processors.
CPP is Cisco’s network processing group for a range of routing platforms.
The CPP group will soon begin development of a next-generation design,
and is seeking talented and driven engineers at all experience levels to
work on this exciting and important opportunity.
This should be a unique opportunity to be part of something very advanced.
Participate in the design of complex, high-performance, and highly integrated ASICs used in Cisco’s networking products.
Responsibilities include:
Architecture definition/analysis and feasibility studies. Detailed micro-architecture specification, RTL logic design, synthesis and timing closure. Must work closely with verification team members to develop test plans and actively participate in the debug phase.
Some involvement in physical design support from floorplan through back-end phases to sign off.
Skills Required:
Experience in high-performance ASIC design. Good understanding of ASIC methodologies and flows.
Hands-on experience with HDL languages and tools, scripting and programming languages (Perl, TCL). Good communications skills and a team player. Networking knowledge preferred, but not essential.
Qualification:
1. High-performance, complex ASIC design experience.
2. Proficiency in contemporary ASIC design methodologies and flows, working knowledge using HDL languages and tools.
3. Good communication and teamwork skills.
Educational Background:
Typically requires MSEE/CS combined with 6-8 years of related experience, or BSEE/CS combined with 8-10+ yrs related experience .
If you are interested, send your resume directly to me at joel@rt6.com so it will arrive the quickest and get immediate attention with the hiring manager.
Joel Steinberg
President- Responsive Technology
www.rt6.com (Bayareastartups)
Referral fees are also being offered ($3000) for names/emails submitted for the following:
ASIC design
FPGA design
ASIC/FPGA Manager
ASIC/FPGA Directors
HS Board design
Firmware/RT/Emb SW
SW QA (RT Embedded)
Analog/RFIC
Also: Physical design/ CAD/ Mask/Layout
Please email me at joel@rt6.com to hear about and have immediate access to gthe hiring managers at other hot openings at Cisco, Marvell, and other hot startups in Silicon Valley.
Job Categories: Cisco |